CMPEN 331 Pennsylvania State University Computer Organization and Design Lab 5

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This lab introduces the idea of the pipelining technique for building a fast CPU. The students will obtain experience with the design implementationand testingof the first fourstages (Instruction Fetch,Instruction Decode, Instruction Execute, Memory) of the five–stagepipelined CPU using the Xilinx design package for FPGAs. It is assumed that students are familiar with the operation of the Xilinx design package forField Programmable Gate Arrays (FPGAs)through the Xilinix tutorial available in the class website.